Design and Implementation of FIR FILTER using MCM Architecture
E.Mallikarjuna, L.S.Devaraj , R.Naresh Naik
Corresponding Author : E.Mallikarjuna.
Dept. of ECE, Intellectual Institute of Technology, Anantapur. India
Email ID : firstname.lastname@example.org
Received : 2015-06-12 Accepted : 2015-07-24 Published : 2015-07-24
Abstract : To Design the low complexity bit-parallel multiple constant multiplications (MCM) operation, many efficient algorithms and architectures have been introduced in the last two decades. The MCM operation has been dominates the complexity of many digital signal processing systems. On the other hand, the digit-serial MCM design has becoming more popular and this design offers alternative low complexity MCM operations albeit at the cost of an increased delay. In this paper we are introducing high level synthesis algorithms, design architectures and CAD tools and also we address the problem of optimizing the gate level area in digit serial MCM design. The experimental results shows the efficiency of digit-serial MCM architectures and the proposed optimization algorithms in the design of MCM operations and finite impulse response filters.
Keywords : 0–1 integer linear programming (ILP), digit-serial arithmetic, finite impulse response (FIR) filters, CSE and GB algorithms, multiple constant multiplication.
Citation : E.Mallikarjuna et al. (2015). Design and Implementation of FIR FILTER using MCM Architecture. J. of Advancement in Engineering and Technology. V3I2. 01 DOI : 10.5281/zenodo.890243
Copyright : © 2018 E.Mallikarjuna. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Journal of Advancement in Engineering and Technology
ISSN : 2348-2931
Volume 3 / Issue 2
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